1. Field of the Invention
The present invention relates to a wafer or a circuit board, each of which is used to perform three-dimensional mounting by being joined to each other, and relates to a joining structure of the wafer or the circuit board.
2. Description of the Related Art
The thinning and miniaturization of an electronic apparatus have been achieved by the miniaturization of components mounted to the electronic apparatus. Conventionally, the miniaturization technique of the components has been largely dependent upon the microfabrication technology of LSI. However, enormous installation investment is required to introduce a finer microfabrication technology of LSI, and hence the introduction of such a technique cannot satisfy the need to reduce product costs. The problem can be solved in such a way that a through-electrode perpendicularly penetrating through the surface of a wafer (silicon and a compound semiconductor) is formed, that electrodes are formed on the front and rear surfaces of the wafer, and that the electrodes of each of the wafers are connected to each other by laminating the wafers. Accordingly, a technique to change conventional planar mounting (two-dimensional mounting) into spatial mounting (three-dimensional mounting) has been developed.
In Japanese Patent Laid-Open No. 11-204939, there is proposed, as a method for laminating the wafers, a method in which after bumps are formed on the wafers, the wafers, with an adhesive applied thereon, are stuck to each other. Further, in the patent document, there is disclosed a method in which metals on the surface, to which the adhesive is applied, are connected to each other by forcing out the adhesive from between the metals. In the patent document, tin-plated terminals, on which the adhesive is applied, are joined to each other while being pressed together. Thereby, the adhesive is forced out from between the metal joining portions, so that the metals are electrically connected to each other. However, a large force is required at the time of pressing the terminals together, and hence the method is unsuitable for minute bumps which are the object of the present invention.
In Japanese Patent Laid-Open No. 10-308415, there is described, as a method for connecting a solder protrusion to a connection electrode on a wiring board without using flux, a method of using a solder protrusion formed by a first protrusion and a second protrusion. In the patent document, a solder protrusion having a two-stage structure formed by the first protrusion and the second protrusion is formed such that the melting temperature of the first protrusion is higher than that of the second protrusion and that the surface area of the first protrusion is two times or more larger than the surface area of the second protrusion. In the method, the connection electrode on the wiring board and the solder protrusion are made to face each other, and are heated at a temperature which is equal to or lower than the melting temperature of the first protrusion and which is equal to or higher than the melting temperature of the second protrusion, while an electronic component is pressed. Since only the second protrusion is melted at the soldering temperature, the second protrusion can be expanded between the first protrusion and the connection electrode on the wiring board by the application of a slight pressing force. Thereby, as described in the patent document, the oxide film on the surface of the second protrusion is broken to expose the intrinsic layer in the second protrusion, so that a desired joining state can be obtained.
In Japanese Patent Laid-Open No. 2002-198485, there is described that first protrusion electrode 15 of first LSI chip 16 is a Sn-3.5Ag solder protrusion containing 96.5% of Tin (Sn) and 3.5% of silver (Ag), and that second protrusion electrode 19 is a protrusion made of nickel (Ni). Thus, second protrusion electrode 19 of second LSI chip 20, which has a small diameter and high hardness, is made to bite into first protrusion electrode 15 of first LSI chip 16, to allow bump 19 of second LSI chip 20 to break through the oxide film formed on the surface of first protrusion electrode 15 of first LSI chip 16, so that first LSI chip 16 and second LSI chip 19 are joined to each other. Thereby, as described in the patent document, there is obtained an advantage in which it is possible to realize a firm joining structure and possible to realize a semiconductor mounting assembly that has excellent temporal stability at high temperature. Further, as also described in the patent document, there is an advantage in which the melting point can be made low, and thereby the processing temperature for joining respective bumps can be set to a low level. However, the role of the protrusion is limited, as described above, and does not play the role of a spacer.
In Japanese Patent Laid-Open No. 2006-59957, there is described a method of using a protrusion, as a method of manufacturing a semiconductor package structure and a semiconductor package, and this method features excellent productivity, and a capability for making thinner and more miniaturized products, and has higher performance. However, the object of the protrusion is to break through a resin layer, and the protrusion does not play the role of a spacer. Further, a low melting point metal is not formed so as to cover the protrusion. Further, in the patent document, in addition to the above described protrusion, the followings are also disclosed about joining particles. The joining particles are arranged and joined at predetermined positions on the surface of a circuit conductor. The joining of the joining particles is performed by a method of ultrasonic welding, welding, soldering, applying a conductive resin, or the like. Then, the surface on which the joining particles are arranged, and a resin layer on which a conductor metal is provided, are arranged so as to face each other. By using a hot press apparatus, the resin layer on which the conductor metal is provided is heated at a predetermined temperature so as to be softened and then heat pressed. Thereby, the joining particles are embedded into the softened resin layer. When the resin layer is further heat pressed, the joining particles, and the conductor metal which is another conductor layer, are brought into contact and joined with each other.
In the case where conventional planar mounting (two-dimensional mounting) is changed into spatial mounting (three-dimensional mounting), it is difficult to fill an adhesive between respective layers, by the conventionally proposed method in which (1) the formation of a connection electrode, (2) lamination and connection, and (3) the filling of the adhesive between the layers, are performed in this order. In particular, when wafers that are used as an ideal form of the three-dimensional mounting are joined to each other, it is difficult to make the adhesive flow uniformly between the layers of wafers of eight inches or more.
On the other hand, it is difficult to control the heating and pressing conditions in the method in which an adhesive is applied to the surface of a metal and in which the metals are joined with each other by forcing out the adhesive from between the metals, that is, in the method in which (1) the formation of a connection electrode, (2) the application of adhesive, and (3) lamination and joining are performed in this order. That is, when the adhesive is applied beforehand between the layers of the wafers, and when the wafers are then heated and pressed, the joining portion is deformed, so that in some cases, the low melting point material used for the joining may be brought into contact with an adjacent joining portion.